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JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Detailed re-configurable PLL data description for Cyclone 10?

Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Apologies,

  1. PLL is sampling the serial-data on rising of scanclk.
  2. PLL Component Scan Chain Order & Scan Chain Bit Order is given.
  3. All 144 bits are addressed.

Please do refer below link.

https://www.intel.com/content/www/us/en/programmable/documentation/sxm1481253171919/pux1489734928671/wgw1489995238792.html

Let me know if need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

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