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JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Detailed re-configurable PLL data description for Cyclone 10?

Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Jens,

Please refer to the attached .pdf file under table 2 that shows the 144 bits info for the Cyclone 10 LP PLL scan chain bitmap. We have been looking into this request internally and we require some time to check which documentation that has the 144 bits information. Even though the documentation stated Cyclone III, the PLL architecture for Cyclone 10 LP and Cyclone IV should be the same as Cyclone III. For details on the PLL Reconfig for Cyclone 10 LP, you can refer to the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altpll_reconfig.pdf

Hopefully this might help to address your needs.

Regards,

Nooraini