CROSS CLOCK vhdl

Hello Guys,

I had done the cross clock domain, I used the FIFO that you sugested me. It works.

About the person that ask me about the frequency, it is 160 MHz, because I need to do the interpolation using 4 random pixels.

I attach here the RTL, maybe it can be usefull to someone else in the future.

Also in the attached file you can see the output of my system.

Thank you.

DABG

It should be understood that this...

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Underflow and overflow circuitry protections are enabled by default to prevent FIFO data corruption. Turning on the option from the FIFO

MegaWizard plug-in disables the protection circuitry.

When the protection circuitry is disabled, writing to a full FIFO can corrupt the FIFO dataand reading from an empty FIFO can return unknown data and produce unpredictable future results; however, when the protection circuitry is disabled, the FIFO megafunction uses fewer device resources.

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does not mean that you shouldn't empty or fill a FIFO. You just can't write to a full FIFO or read from an empty FIFO without corrupting the contents. And the obvious reason why is that the read or write counter will roll over.

So, you can either instruct the megawizard to perform protection for you or you can perform the protection yourself (which is what I typically do). Typically you have the empty and full signals anyway so you can perform flow control. It's certainly not hard to gate your write and read signals with the full and empty signals.

Jake

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It seems that altera has two remediies for their old warning:

1) an almost_empty flag

2) protection circuitry(extra logic)

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I see what you mean. I wonder if this is the same for LOOKAHEAD style fifos.

But the above problem can surely be avoided (on the read side at least) by anding any read control with !empty, then you will never try and read from an empty fifo.

It seems that altera has two remediies for their old warning:

1) an almost_empty flag

2) protection circuitry(extra logic)

This what they say(dc fifo user guide)

--- Quote Start ---

Underflow and overflow circuitry protections are enabled by default to prevent FIFO data corruption. Turning on the option from the FIFO

MegaWizard plug-in disables the protection circuitry.

When the protection circuitry is disabled, writing to a full FIFO can corrupt the FIFO dataand reading from an empty FIFO can return unknown data and produce unpredictable future results; however, when the protection circuitry is disabled, the FIFO megafunction uses fewer device resources.

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Whats wrong with emptying a FIFO? if you have proper data flow control, and dont just expect valid data on every clock cycle (ie. you have a data_valid control signal) you shouldnt have a problem.

with video, you get about 80/20 valid data to blanking ratio, with the blanking region not valid. You get a long period of inactivity that is likely to empty your fifos.

What is the reason for not allowing fifos to get empty? I can understand the full problem (espcially if its video, you will lose syncronisation on the data) with pixels being dropped.

Hi,

However, Altera adviced against getting any fifo full or empty during normal operation. Isn't this still the case?

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I frequently pass video across clock domains using dual-clock fifos. Simply use the empty signal on the read side of the FIFO as a datavalid or clock enable. All other signals should be passed as data through the FIFO.

Jake

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Thats exactly what I do - works great.

I see you mention you are doing billinear interpolation.. why do you need a 160 MHz clock? I get the feeling you are buffering up a line and then doing 4 reads to get your 4 pixel values.

If you're only doing billinear interpolation (and nothing else) you can run it at 40MHz and just cope with a 1 line latency (which you'll get at 160MHz anyway). The pixels you need come from a line delay memory and a few registers, all clocked at input pixel frequency.

Not knowing the full spec of the system, I cant really comment. But I assume you have a billinear interpolate as part of a Warp function?

I frequently pass video across clock domains using dual-clock fifos. Simply use the empty signal on the read side of the FIFO as a datavalid or clock enable. All other signals should be passed as data through the FIFO.

Jake

Having said that I foresee difficulty in flow control because your fifo clks are not locked.

You will need to have a plan for that. I suggest not passing data valid(if I understand its purpose). Instead use it as write enable. Watch your fifo getting near empty, stop reading and generate your own data valid now accordingly in the new domain.

As such fifo is not allowed to get full either unless it is too shallow because your read clk is free to read at any clk edge.