Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCROSS CLOCK vhdl
Hello Everybody, In my application I receive images from a camera that uses CAMERA LINK protocol (100 fps). The camera generates its own 40 MHz pixel clock. All the data's from the camera ...
Altera_ForumHonored Contributor
Honored ContributorHello,
It means that for cross clock the data I should use the FIFO, and to cross clock domain the signal LVAL, FVAL and DVAL I should use 2-ff stage synchronizer? Can I mix the 2 techniques?:confused: ---------------------------------------------------------- clk domain 1 // >>---------------------->>// clock domain 2 ----------------------------------------------------------- data[9:0] ----------->> fifo ------------>> data_sync[9:0] FVAL --------------->> 2-ff sync------->> FVAL_sync DVAL --------------->> 2-ff sync------->> DVAL_sync LVAL --------------->> 2-ff sync------->> LVAL_sync fval=frame valid dval=data valid lval=line valid Thank you, DABG
