CROSS CLOCK vhdl

Hello,

Thank you KAZ and JACK,

Yes, the 2nd option that explains Jake is the easiest, however the problem is that I am using a Cyclone 2, and the CLK_40MHz that comes from the camera is not phisically connected to a dedicated CLK pins. (We designed the board, and we did not take it not account, ups:o)

"only dedicated CLK pins on the FPGA

can be connected to clock input ports of PLLs" Cyclone 2 manual.

And I got this error after compiling:

"Port type INCLK of the PLL is assigned to a location which is not

connected to port type INCLK of any PLL on the device".

I guess I will try to develop the option that use the FIFO.

I need to work at 160MHz because then I am going to store the last 20 lines of the image in the internal memory (m4k), and I need to read 4 random pixels to implement a Bilinear Interpolation.

Still I am confused with the two flip flop stage synchronizer, in which cases are them useful?

Thank you.