CROSS CLOCK vhdl

Hi,

The fifo circuitry contains hidden multistage synchronisers(defaults to 2 or use more, setup by you in the megawizard). So don't worry about what others say. Use the fifo to read/write. The main headache is getting the flow under control, this depends on input burstiness, fifo size, fill-level ...etc. Try it and you will learn. I assume you have clk enable(or data valid at input) and you expect steady 24MHs data rate at fifo output.

Looking at your picture, I can see clk is 160MHz out of PLL. There is some confusion here. I assume you first want to cross from 40MHz to 24MHz...nevertheless if you want to cross from 40 to 160 the same rule applies but your data cannot change rate unless you interpolate or decimate.

It looks that Your design produces 160MHz but doesn't seem to use it.

If your intention is cross from 40 to 160(rather than 24) then you can do that directly using fifo or it might be a good idea to have another clk 40MHz from PLL(synchronised with 160) and read fifo out as this eases the problem of flow control, though these two clks are not locked to each other i.e. they will get drift away with time and you still need some flow control.

Once you want to go in 160MHz domain, then you either keep data rate(valid every 4 clks) or upsample by 4 if you want it valid every clk(depends on your purpose)