CROSS CLOCK vhdl

Directly crossing clock domains with a synchronizer is useful in many cases. Most particularly when you are passing single control signals between clock domains or sampling an asynchronous signal at low data rates.

The reason two registers are used is because when you sample the signal in the first flip-flop, there is the possibility that the input is rising or falling which can push the flip-flop into metastability. Latching the signal into a second flip-flop increases the probability that the latched output signal will be stable. Adding even a third flip-flop increases the probability more.

This type of resynchronization is not as useful when you are dealing with large data buses. It certainly can be done under the right circumstances and constraints but in your particular case, it's just not worth the effort.

Jake