CROSS CLOCK vhdl

Having said that I foresee difficulty in flow control because your fifo clks are not locked.

You will need to have a plan for that. I suggest not passing data valid(if I understand its purpose). Instead use it as write enable. Watch your fifo getting near empty, stop reading and generate your own data valid now accordingly in the new domain.

As such fifo is not allowed to get full either unless it is too shallow because your read clk is free to read at any clk edge.