CROSS CLOCK vhdl

Anything that passes through dc fifo will pass through the fifo's two stage synchroniser.

If you want to pass other signals with data just add an extra bit to width of fifo for every extra bit you want to pass.

You may use a signal at write only and not pass it e.g. data valid can be used as write enable to fifo without the need to pass it through if at the read side every clk is valid data, this seems unlikely in your case. So it depends on your application.