CROSS CLOCK vhdl

My thoughts:

1 - Truly the dual-clock FIFO is the easiest, most reliable method for cross-domain bus data transfer. If you just had one or two signals it might be a different story.

2 - A second option (assuming you are crossing from 40Mhz to 160Mhz) would be to use the 40MHz clock as the input to a PLL to produce your 160MHz clock. Then, your two clock domains would actually be related. In this case you can cross the clock domains fairly easily without a FIFO.

3 - The third option alluded to by kaz is to cross from 40MHz to 160MHz but where the 160MHz clock is not related to the 40MHz. In this case, I still vote for the dual-clock FIFO. You could perform oversampling but 4x is kind of a low oversampling rate. And of course you would have to write the oversampling block which I suspect you don't really want to do.

Recommendation: Use the dual-clock FIFO unless your two clock domains are related. In which case I'd still use the FIFO unless you are really trying to save RAM resources.

Jake