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Altera_Forum
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17 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 and bank6 to 3.3V? The handbook says that they should be connect to 2.5V, but if I do so, the other IO pins in this two banks can not be connected to the 3.3V external chips. how can I deal with it?

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    From the datasheet, it's clear that Stratix II needs 2.5V VCCIO in left and right IO banks. 2.5V IO standard can interface 3.3V on input and - by specification - only 3.3V LVTTL but but not 3.3V LVCMOS on output. Thus it depend on the input characteristics of conncted chips, if they are satisfied with 2.5V logic level. Also left and right bank LVDS inputs may possibly operate with a higher VCCIO and reduced performance. But there is no specification. It would be better to group VCCIO according to interface voltage needs. When ask, if pins in bank 5 and 6 can be used for 3.3V, why not using one bank for LVDS and the other for LVCMOS? When mixing single-ended and differential IO in a bank, a lot of pins can't be used due to placement rules.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for reply!

    Profit from your suggestion, I have changed my design.Now the IO bank 5 and 6 are used only for Lvds receiving and the signal-ended signals are all moved to other banks. And I tied the VCCIO for bank 5 and 6 to 2.5V, VREFB to GND. I wish I have done nothing wrong!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The best way is to check your pin assignments with Quartus software to validate that all intended pin assignments are possible and placement rules are kept.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    To do that checking, I make a simple dummy design that takes all the inputs into a really wide AND gate.

    That AND Gate then drives the enable on a really long counter that drives the outputs.

    If I have multiple clocks in the design, then I just make multiple of these "designs".

    Run it through the tools, and check to see that there are NO assignment voilations.

    10 minutes max!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hello,wynn.

    it's clear that Stratix II DD support both 2.5V LVDS and 3.3V LVDS according to datasheet, why not apply 3.3V LVDS?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    why not apply 3.3V LVDS

    --- Quote End ---

    Cause Stratix II does not "support both 2.5V LVDS and 3.3V LVDS", but LVDS with VCCIO of 2.5V in left and right bank and with 3.3V VCCIO in top and bottom bank. I admit, that this is a bit complicated, but it has been already clarified in the discussion, if you kindly read the contributions in detail.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    hello FvM,

    ur right .Stratix II only support 2.5V LVDS on left-right banks and 3.3V LVDS on top-bottom banks. I got myself mixed and confused that. :-)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi there,

    I found myself in a similar situation as wynn but couldn't use the solutions suggested in this thread. Should I open a new thread?

    ... anyway, I am doing a quick modification to an existing board just to change a few I/O on bank 5 from LVCMOS to LVDS). This board uses Cyclone III and has 3.3 volts on all VCCIO. What will happen if I tell Quartus II the VCCIO for bank 5 is connected to 2.5v so that the design can compile(in fact it's still connected to 3.3v on the board) ? would it fry the chip when I load the design to the board? All the lvds signals are looped back to bank 5 directly.

    Thanks and any comment will be appreicated.

    Hua
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Although the datasheet doesn't cover this case, I wouldn't expect damage of the chip. Most likely the LVDS receiver are operational with reduced performance (common mode range, speed).

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you for your reply, FvM. What about those single ended I/O on bank 5? The power is 3.3 volts and the Quartus II is told 2.5 volts. What kind of effect will it be on those I/Os?

    Thanks again.

    Hua