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Altera_Forum
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17 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thank you for your reply, FvM. What about those single ended I/O on bank 5? The power is 3.3 volts and the Quartus II is told 2.5 volts. What kind of effect will it be on those I/Os?

Thanks again.

Hua