Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hello FvM,

ur right .Stratix II only support 2.5V LVDS on left-right banks and 3.3V LVDS on top-bottom banks. I got myself mixed and confused that. :-)