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Altera_Forum
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17 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 and bank6 to 3.3V? The handbook says that they should be connect to 2.5V, but if I do so, the other IO pins in this two banks can not be connected to the 3.3V external chips. how can I deal with it?

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  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    No effect at all. Nothing is changed in the hardware when specifying either 3.3V or 2.5V VCCIO.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

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    When mixing single-ended and differential IO in a bank, a lot of pins can't be used due to placement rules.

    --- Quote End ---

    Hi,FvM.Could you tell me some more details? Thank you very much.