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Honored Contributor
Honored ContributorCan I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?
hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- When mixing single-ended and differential IO in a bank, a lot of pins can't be used due to placement rules. --- Quote End --- Hi,FvM.Could you tell me some more details? Thank you very much.
