Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

From the datasheet, it's clear that Stratix II needs 2.5V VCCIO in left and right IO banks. 2.5V IO standard can interface 3.3V on input and - by specification - only 3.3V LVTTL but but not 3.3V LVCMOS on output. Thus it depend on the input characteristics of conncted chips, if they are satisfied with 2.5V logic level. Also left and right bank LVDS inputs may possibly operate with a higher VCCIO and reduced performance. But there is no specification. It would be better to group VCCIO according to interface voltage needs. When ask, if pins in bank 5 and 6 can be used for 3.3V, why not using one bank for LVDS and the other for LVCMOS? When mixing single-ended and differential IO in a bank, a lot of pins can't be used due to placement rules.