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Altera_Forum's avatar
Altera_Forum
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18 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for reply!

Profit from your suggestion, I have changed my design.Now the IO bank 5 and 6 are used only for Lvds receiving and the signal-ended signals are all moved to other banks. And I tied the VCCIO for bank 5 and 6 to 2.5V, VREFB to GND. I wish I have done nothing wrong!