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Altera_Forum
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17 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi there,

I found myself in a similar situation as wynn but couldn't use the solutions suggested in this thread. Should I open a new thread?

... anyway, I am doing a quick modification to an existing board just to change a few I/O on bank 5 from LVCMOS to LVDS). This board uses Cyclone III and has 3.3 volts on all VCCIO. What will happen if I tell Quartus II the VCCIO for bank 5 is connected to 2.5v so that the design can compile(in fact it's still connected to 3.3v on the board) ? would it fry the chip when I load the design to the board? All the lvds signals are looped back to bank 5 directly.

Thanks and any comment will be appreicated.

Hua