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Altera_Forum
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18 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

To do that checking, I make a simple dummy design that takes all the inputs into a really wide AND gate.

That AND Gate then drives the enable on a really long counter that drives the outputs.

If I have multiple clocks in the design, then I just make multiple of these "designs".

Run it through the tools, and check to see that there are NO assignment voilations.

10 minutes max!