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Altera_Forum
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17 years ago

Can I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?

hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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why not apply 3.3V LVDS

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Cause Stratix II does not "support both 2.5V LVDS and 3.3V LVDS", but LVDS with VCCIO of 2.5V in left and right bank and with 3.3V VCCIO in top and bottom bank. I admit, that this is a bit complicated, but it has been already clarified in the discussion, if you kindly read the contributions in detail.