Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCan I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?
hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- why not apply 3.3V LVDS --- Quote End --- Cause Stratix II does not "support both 2.5V LVDS and 3.3V LVDS", but LVDS with VCCIO of 2.5V in left and right bank and with 3.3V VCCIO in top and bottom bank. I admit, that this is a bit complicated, but it has been already clarified in the discussion, if you kindly read the contributions in detail.
