Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCan I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?
hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 ...
Altera_ForumHonored Contributor
Honored ContributorAlthough the datasheet doesn't cover this case, I wouldn't expect damage of the chip. Most likely the LVDS receiver are operational with reduced performance (common mode range, speed).
