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Altera_Forum
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Honored Contributora strange problem!
module zhengxing(clk_200M,
rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low=2'b00, wait_high=2'b01, high=2'b10, wait_low=2'b11; always @ (posedge clk_200M or posedge rst) if(rst==1) begin counter<=0; data_out<=0; state<=low; end else case(state) low:if(counter>=3) begin data_out<=0; state<=wait_high; end else begin counter<=counter+1; // data_out<=1; state<=low; end wait_high:if(data_in==1) begin state<=high; counter<=0; ///data_out<=0; end else begin state<=wait_high; counter<=0; //data_out<=0; end high:if(counter>=3) begin data_out<=1; state<=wait_low; end else begin state<=high; counter<=counter+1; end wait_low:if(data_in==0) begin state<=low; counter<=0; end else begin state<=wait_low; counter<=0; end default:state<=low; endcase endmodule there is no error in it.and the simulation is also right ,but when it is in the fpga ,it doesn't work.and the out port is always high ; i don't know it's why! who can help me? thank you!19 Replies
Altera_Forumhave had simular problems, problem is don't remember how i got around them all. some just went away when i changed something. :rolleyes:
one i remember: check rtl veiwer and see if it is correct. have found corrupted rtl. got around this by clicking on a block and updataing 'all' blocks. another problem went away when i installed singnal tap to watch it. you have indicated that you have signal tap installed. what does it say? what does the floor plan show for that pin?- Altera_Forum
Your code should work, and the data_out should react on the change of data_in. There are a number of possible causes that you should make sure to work:
1) Check that the polarity of the rst signal is OK as pletz suggests. (You seem to have done this). 2) Make sure that your clock speed is not too high. 200MHz is high for a Cyclone-II. It depends on the specific configuration of your circuit if this will work or not... 3) Make sure that the output can change as pletz suggested. (You seem to have checked this too). 4) You should check that your data_in signal is OK. You could test your design by having data_in connected to a switch, the state to two LEDs and the data_out to a LED. You should be able to see the states of the wait_high and wait_low when you push on the data_in button. Your data_out LED should follow your data_in button. Hope this helps - Altera_Forum--- Quote Start --- 200 MHz, generated from your PLL, is a rather fast clock for a Cyclone-II. 1) Make sure with the TimeQuest Timing Analyzer that your design meets the timing requirements. (200 MHz means a 5nsec clock period). 2) You could first try to feed your design with a slower clock and debug it. You could take your external clock signal for that. That is probably much lower than the 200 MHz. --- Quote End --- i also try it with 20M,it doesn't work ! this is the a picture of timing analyzer!
- Altera_Forum--- Quote Start --- the signal of clk_200M is from pll ,it's 200M,and data_in is the input of sqare wave ,and the rst is the input of reset, the out _data is the output of square wave afte this module ,and the square wave of data_in is under 10M, --- Quote End --- 200 MHz, generated from your PLL, is a rather fast clock for a Cyclone-II. 1) Make sure with the TimeQuest Timing Analyzer that your design meets the timing requirements. (200 MHz means a 5nsec clock period). 2) You could first try to feed your design with a slower clock and debug it. You could take your external clock signal for that. That is probably much lower than the 200 MHz.
- Altera_Forum--- Quote Start --- Hi, did you capture the data_in with signaltap ? Which clock did you use for signaltap ? Kind regards Gerd --- Quote End --- i use 200M in the signal tap,so it should be captured !
- Altera_Forum--- Quote Start --- oh ! i changed the name of this module in my project in this afternoon, and it's name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine, it doesn't work.but when i press the reset ,the register of counter and data_out is changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.and the data_out is always high! --- Quote End --- Hi, did you capture the data_in with signaltap ? Which clock did you use for signaltap ? Kind regards Gerd
- Altera_Forum--- Quote Start --- Hi. I assume you have your block conneted in the right way. Did you check your reset signal polarity ? What is your clock frequency and what is the toggling rate of your data_in? Kind regards Gerd --- Quote End --- oh ! i changed the name of this module in my project in this afternoon, and its name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine,but it doesn't work.when i press the reset ,the register of counter and data_out is be changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction. the signal of clk_200M is from pll ,it's 200M,and data_in is the input of sqare wave ,and the rst is the input of reset, the out _data is the output of square wave afte this module ,and the square wave of data_in is under 10M,
- Altera_Forum
oh ! i changed the name of this module in my project in this afternoon, and it's name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine, it doesn't work.but when i press the reset ,the register of counter and data_out is
changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.and the data_out is always high! - Altera_Forum--- Quote Start --- oh! i've changed the name of the module ,and its name is zh.v ,and use it in zhengxing.bdf --- Quote End --- Hi. I assume you have your block conneted in the right way. Did you check your reset signal polarity ? What is your clock frequency and what is the toggling rate of your data_in? Kind regards Gerd
- Altera_Forum--- Quote Start --- Hi, I did not see your verilog file ( in your first post) in the qsf. Are you using the zhengxing.bdf ? Is your reset signal connected ? Polarity ? Kind regards Gerd --- Quote End --- oh! i've changed the name of the module ,and its name is zh.v ,and use it in zhengxing.bdf
