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Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, I did not see your verilog file ( in your first post) in the qsf. Are you using the zhengxing.bdf ? Is your reset signal connected ? Polarity ? Kind regards Gerd --- Quote End --- oh! i've changed the name of the module ,and its name is zh.v ,and use it in zhengxing.bdf
