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Altera_Forum
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17 years ago

a strange problem!

module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_Forum's avatar
Altera_Forum
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17 years ago

oh ! i changed the name of this module in my project in this afternoon, and it's name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine, it doesn't work.but when i press the reset ,the register of counter and data_out is

changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.and the data_out is always high!