Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- oh! i've changed the name of the module ,and its name is zh.v ,and use it in zhengxing.bdf --- Quote End --- Hi. I assume you have your block conneted in the right way. Did you check your reset signal polarity ? What is your clock frequency and what is the toggling rate of your data_in? Kind regards Gerd
