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Altera_Forum
Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored Contributorhave had simular problems, problem is don't remember how i got around them all. some just went away when i changed something. :rolleyes:
one i remember: check rtl veiwer and see if it is correct. have found corrupted rtl. got around this by clicking on a block and updataing 'all' blocks. another problem went away when i installed singnal tap to watch it. you have indicated that you have signal tap installed. what does it say? what does the floor plan show for that pin?
