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Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- the signal of clk_200M is from pll ,it's 200M,and data_in is the input of sqare wave ,and the rst is the input of reset, the out _data is the output of square wave afte this module ,and the square wave of data_in is under 10M, --- Quote End --- 200 MHz, generated from your PLL, is a rather fast clock for a Cyclone-II. 1) Make sure with the TimeQuest Timing Analyzer that your design meets the timing requirements. (200 MHz means a 5nsec clock period). 2) You could first try to feed your design with a slower clock and debug it. You could take your external clock signal for that. That is probably much lower than the 200 MHz.
