--- Quote Start ---
Hi.
I assume you have your block conneted in the right way. Did you check your reset signal polarity ? What is your clock frequency and what is the toggling rate of your data_in?
Kind regards
Gerd
--- Quote End ---
oh ! i changed the name of this module in my project in this afternoon, and its name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine,but it doesn't work.when i press the reset ,the register of counter and data_out is
be changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.
the signal of clk_200M is from pll ,it's 200M,and data_in is the input of sqare wave ,and the rst is the input of reset, the out _data is the output of square wave afte this module ,and the square wave of data_in is under 10M,
Honored Contributor
