Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributora strange problem!
module zhengxing(clk_200M, rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter; reg [1:0]state; parameter low...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, did you capture the data_in with signaltap ? Which clock did you use for signaltap ? Kind regards Gerd --- Quote End --- i use 200M in the signal tap,so it should be captured !
