152 Results
Why are the R-Tile AXI Multichannel DMA IP Design Example DMA Queues stuck when the Gen5 IP configuration links downgrade to Gen4 or lower speeds?
Description Due to a problem in the Quartus® Prime Pro software version 25.3.1 and earlier, the AXI Multichannel DMA IP Queues will stick if the Gen5 configuration of the IP is link downgrades to G...36Views0likes0CommentsWhy is there critical Design Assistant violation reported at Synthesis stage after Scalable Scatter-Gather DMA IP DMA PCIe Mode Example Design compilation?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, critical Design Assistant violation may be reported after Scalable Scatter-Gather DMA IP DMA PCIe M...60Views0likes0CommentsWhy does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP&n...96Views0likes0CommentsWhy does the H2D *ST device port of the Scalable Scatter-Gather DMA FPGA IP send non-contiguous data in the DMA PCIe mode for Completion TLPs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the Scalable Scatter-Gather DMA FPGA IP DMA PCIe Mode can only support incoming Completion TLPs for Mem R...62Views0likes0CommentsWhy does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1, the BAM in the AXI Multichannel DMA IP for PCI Express* may fail to return Completion TLPs in simulation once the c...13Views0likes0CommentsWhy is corrupted receiving data seen on the Bursting Avalon-MM Master (BAM) Interface when using Multi Channel DMA FPGA IP for PCI Express*?
...ulti-Channel DMA FPGA IP for PCI Express, particularly if extensive backpressure is applied to the incoming data stream. Resolution A patch is available to fix this problem for the Quartus® Prime P...123Views0likes0CommentsWhy does the PCIe* DMA Controller Stratix® 10 FPGA IP send two continuous MSI interrupts for the DMA operation?
Description Due to a problem in the PCIe* DMA Controller Stratix® 10 FPGA IP, the DMA controller will send out two continuous MSI interrupts: one for the DMA Read MSI vector and the other for the DMA...31Views0likes0CommentsWhy does the Multi-Channel DMA FPGA IP for PCI Express* stall or stop operating when the Q_SIZE parameter is configured to 0x10?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.2 and later, the Multi-Channel DMA FPGA IP for PCI Express* may stall or cease operation when the Q_SIZE p...46Views0likes0CommentsWhy do I see generation error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design using Quartus® Prime Pro Edition software version 24.1 for Windows*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and onwards for Windows, you may see the below error message when generating F-Tile Multi Channel DMA IP for P...43Views0likes0CommentsWhy are there ongoing DMA transactions at the Scalable Scatter-Gather DMA IP's device port even after the completion of the device port soft pause and soft reset sequence flow?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, the Scalable Scatter-Gather DMA IP may observe an ongoing DMA transaction for the device port when t...39Views0likes0Comments
