errata
187 TopicsWhy o_rx_pcs_fully_aligned does not assert for 40GE-4 Advanced mode F-Tile Ethernet Hard IP design when Custom Ethernet line rate > 63Gbps?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might observe o_rx_pcs_fully_aligned does not assert for the F-Tile Ethernet Hard IP design with below configurations: Advanced mode: Enabled Ethernet mode: 40GE-4 Custom Ethernet line rate: > 63 Gbps Resolution There is no workaround. There is no fix planned in the future. When advanced mode enabled for 40GE-4 design, supported custom Ethernet line rate is: 41.25~63 Gbps.41Views0likes0CommentsHow do I enable debug endpoint for transceiver toolkit (ADME) for the F-Tile 25G Ethernet Soft-IP to use the Transceiver Toolkit?
Description The F-Tile 25G Ethernet IP (alt_e25_f) does not expose the "Enable debug endpoint for transceiver toolkit" option in the IP Parameter Editor GUI. As a result, users cannot enable Transceiver Toolkit access through the standard IP configuration interface. Resolution To enable debug endpoint for transceiver toolkit for the F-Tile 25G Ethernet IP, use the following workaround: To enable the debug endpoint for the Transceiver Toolkit, use the following workaround: Open the .ip file for the F-Tile 25G Ethernet Soft IP. Locate the ENABLE_ADME_GUI parameter. Change its value from 0 to 1. Save the .ip file. Regenerate the IP. Note: This workaround modifies a hidden parameter that is not officially available in the GUI. The parameter implementation may change in future releases. After upgrading Quartus® Prime software, verify that the functionality continues to operate as expected.17Views0likes0CommentsWhy does EMIF for HPS LPDDR4 fail calibration on the Agilex® 5 FPGA and SoC FPGA?
Description In the Quartus® Prime Pro Edition Software 24.3, when configuring the Agilex® 5 FPGAs and SoC FPGAs with the EMIF for HPS IP and LPDDR4 device implemented as dual rank (2 chip selects), dual channels (i.e., 4 dies each being 16 Gbit in density), calibration can fail. Resolution This issue is fixed in 24.3.1 Quartus® Prime Pro Edition Software release. quartus-24.3-0.11-windows.exe quartus-24.3-0.11-linux.run quartus-24.3-0.11-readme.txt109Views0likes0CommentsWhy is the eCPRI FPGA IP unable to run on hardware using Stratix® 10 E-Tile with the Nios® V Processor for FPGA and turn on the interworking function (IWF)?
Description Due to a problem in the eCPRI FPGA IP version 3.0.2 in the example design, you may find that there is an error shown at the 10G transaction after changing the dynamic reconfiguration process from 25G to 10G. Resolution There is currently no plan to fix this behavior in a future Quartus® Prime release.85Views0likes0CommentsWhy Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled the active serial programming feature. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.309Views0likes0CommentsWhy are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.72Views0likes0CommentsWhy cannot I use the Transceiver Toolkit in a Dual Simplex design for Agilex® 5 FPGAs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and earlier, Transceiver Toolkit (TTK) is currently not supported for Dual Simplex designs for Agilex® 5 FPGAs. As a result, users may not be able to detect the instance through the System Console or bring up the TTK, which can also impact register access and debugging activities. Resolution This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.1.95Views0likes0CommentsWhy are tx_reset_ack and rx_reset_ack signals not going high in my dual simplex design?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and earlier, you will observe a problem where the tx_reset_ack and rx_reset_ack signals do not go high when you enable the Avalon® memory-mapped interface only for TX Simplex IP or only for RX Simplex IP in your Dual Simplex design. Resolution To work around this problem, you need to enable the Avalon memory-mapped interface for both TX and RX Simplex IP. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.96Views0likes0CommentsWhy is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.1.115Views0likes0CommentsWhy is there a mismatch between the sideband information field of the Scalable Scatter-Gather DMA IP D2H ST responder descriptor and the error bit of the d2h_st_tuser signal?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, when Enable TUSER to SOP mapping feature for D2H_ST Port parameter is disabled and the D2H ST DMA data transfer is not aligned to the D2H ST device port data width, the Scalable Scatter-Gather DMA IP may observe incorrect sideband information (user-defined error) of the D2H ST responder descriptor as compared to the error bit of D2H AXI-ST Subordinate d2h_st_tuser input signal. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.56Views0likes0Comments