Why am I seeing some packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, 25.3 and 25.3.1, you may see traffic failures with packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs. Resolution Add the solution or the workaround to fix the problem or bug. Additional Information Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why am I seeing linkup problem for the GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) multirate IP for HVIO PLL enabled 25G rate designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see linkup problem for the GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) multirate designs. This problem may happen when using 25G multirate designs with HVIO PLL option enabled. Resolution Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why o_rx_pcs_fully_aligned does not assert for 40GE-4 Advanced mode F-Tile Ethernet Hard IP design when Custom Ethernet line rate > 63Gbps?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might observe o_rx_pcs_fully_aligned does not assert for the F-Tile Ethernet Hard IP design with below configurations: Advanced mode: Enabled Ethernet mode: 40GE-4 Custom Ethernet line rate: > 63 Gbps Resolution There is no workaround. There is no fix planned in the future. When advanced mode enabled for 40GE-4 design, supported custom Ethernet line rate is: 41.25~63 Gbps.Why am I seeing Deterministic Latency Accuracy problems when using Inter-protocol Designs in the GTS Dynamic Reconfiguration Controller IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, you may inter-protocol GTS Ethernet Hard IP with PTP and GTS CPRI IP in GTS Dynamic Reconfiguration Controller IP designs. Resolution Currently, there is no workaround for this problem. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software. Related IP Core GTS Dynamic Reconfiguration Controller IP GTS Ethernet Hard IP with PTP GTS CPRI IP
Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the MAC TX of the F-Tile Ethernet FPGA Hard IP halt its transmission of control frames (0x8808) upon receiving PAUSE frames from the link partner?
Description According to Annex 31B.1 of the IEEE802.3 specification, it is noted that the pause operation does not inhibit the transmission of MAC control frames. However, the current implementation of the F-Tile Ethernet FPGA Hard IP mechanism for handling Ethernet frames is not aligned with this specification, as we pause the transmission of all Ethernet frames indiscriminately, regardless of their type. Users wishing to transmit PFC or SFC frames can utilize the SFC/PFC frame generation within HIP, facilitated by register configuration. It's important to note that while our system supports these specific frames, the IEEE specification includes a broader range of control frame types, as outlined in Annex 31A, which HIP does not generate. Alternatively, customers can configure the F-Tile Ethernet FPGA Hard IP to not halt traffic transmission upon receiving Pause frames. Instead, they can utilize the o_pause signal to make transmission decisions at the user end, particularly regarding the transmission of any control frames. Resolution There is no workaround for this problem.Why does the AXI-Lite interface read 'x' in simulation when attempting to access the 'Stat' status registers for the 50g/100g/200g and 400g rates when using the Ethernet Subsystem FPGA IP?
Description Due to a problem in the Ethernet Subsystem FPGA IP version 23.3, the user will be unable to access any status registers using AXI-Lite. Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Ethernet Subsystem FPGA IP.Why are packet counters rolling over within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, the packet counters within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP will roll over when small back-to-back packets are encountered, and the packet counters are nearing the saturated value (i.e., all F’s). Resolution There is no workaround for this problem. This problem has been fixed in version 23.2 of the Intel® Quartus® Prime Pro Edition Software.Why is the eCPRI FPGA IP unable to run on hardware using Stratix® 10 E-Tile with the Nios® V Processor for FPGA and turn on the interworking function (IWF)?
Description Due to a problem in the eCPRI FPGA IP version 3.0.2 in the example design, you may find that there is an error shown at the 10G transaction after changing the dynamic reconfiguration process from 25G to 10G. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the CPRI Intel® FPGA IP Design Example for 24G variants with the Intel® Stratix® 10 L/H-Tile device fail to simulate when using the Cadence Xcelium* simulator?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see the CPRI Intel® FPGA IP Design Example for 24G variants with the Intel® Stratix® 10 L/H-Tile device fails to simulate when using the Cadence Xcelium* simulator. Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.