Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies?
Description Due to a problem in In the Intel® Quartus® Prime Pro Edition Software versions 22.2 and earlier, you might observe the F-tile Reference and System PLL clocks Intel® FPGA IP fails to lock at: 999.9 MHz with the reference clock frequency set as 323.2 MHz. 506.88 MHz with the reference clock frequency set as 245.76 MHz. Resolution To work around this problem, you need to do the following steps: In the project navigator, double-click the OPN (ordering part number). In the pop-out window, click the “Device and Pin Options” button. In the “General” category, change the “Configuration clock source” parameter from “Internal Oscillator” to: 100 MHz OSC_CLK_1 pin, or 125 MHz OSC_CLK_1 pin Recompile the design. Provide an external reference clock with the correct frequency to the OSC_CLK_1 pin. The “OSC_CLK_1” pin location can be found in the schematics of your development kit. Note: for Intel Agilex® F-tile devices with OPNs that end with the suffix VR0, VR1, and VR2, you need to use Intel® Quartus® Prime Programmer version 21.4 to get the above workarounds working.What are the special requirements of Intel Agilex® 7 F-Tile devices reference clocks?
Description The Intel Agilex® 7 F-Tile devices reference clocks have special requirements that users must follow. Otherwise, your design will work abnormally, and transceivers might experience performance degradation. FHT Reference Clock: You must provide a stable and running reference clock to FHT PMA at device configuration. Otherwise, it will cause FHT PMA lane performance degradation. Once the FHT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FHT PMA lane performance degradation, and you must reconfigure the device to get the design working normally. The FHT reference clock stable definition is specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet. FGT Reference Clock: When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You must provide a stable and running reference clock to FGT at device configuration. Otherwise, it will cause FGT PMA lane performance degradation. Once the FGT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FGT PMA lane performance degradation. When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You can provide a stable and running reference clock to FGT after device configuration. After the FGT reference clock is up, it can be inactive. The FGT reference clock stable definition is specified in Intel Agilex 7 FPGAs and SoCs Device Data Sheet. System PLL Reference Clock: When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You must provide a stable and running reference clock to the system PLL at device configuration. Otherwise, the system PLL will not lock, and you must reconfigure the device to get the device working normally. Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally. When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You can provide a stable and running reference clock to system PLL after device configuration. Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally. The System PLL reference clock stable definition Must adhere to the F-Tile FGT Reference Clock Input Specifications specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet. Reference clock maximum period jitter must be less than +/-2.5%. For more details, please refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. Resolution Users must adhere to the aforementioned requirements without any exceptions.Why is not ping continuous and the packets are getting missed when using Triple Speed Ethernet Intel® FPGA IP with 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS core variation?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you might see ping is not continuous and the packets are getting missed when using Triple Speed Ethernet Intel® FPGA IP with 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS core variation. The cause of this problem is that 1000BASE-X transceiver truncates first byte of preamble and replaces it with IDLE byte due to the "EVEN" alignment in Clause 36. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 23.1.Why do the Agilex™ 7 FPGA devices fail to reconfigure after the F-tile System PLL reference clock has a temporary loss?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1 and earlier, if your F-tile System PLL reference clock experiences discontinuity or a temporary loss condition, you might observe that the Agilex™ 7 FPGA device fails to reconfigure. Altera recommends you provide a stable reference clock throughout the design operation once your reference clock for the F-tile System PLL is available. If you cannot adhere to this, you must reconfigure the device. Resolution To work around this problem, you should try configuring your device again if your first reconfiguration fails.Why does toggling p0_pin_perst_n_i fail to reset PCI Express links in the Agilex™ 5 ES devices in the Quartus® Prime Pro Edition Software version 24.1?
Description For a PCIe link in a transceiver bank, there are two pins in HVIO banks with optional function as pin perst for the PCIe link. You can connect PERST# to either one of the reset pins. For the reset pin not used as PERST#, it can be used as a generic HVIO signal. For example, if pin PIN_PERST_N_CVP_L1A_0 in Bank 5A is assigned as PERST# for the PCIe link in Bank L1A, pin PIN_PERST_N_CVP_L1A_1 in Bank 5B can be assigned as a generic HVIO signal. Due to a problem in the ES devices, assigning any of the two reset pins as PERST# fails to reset the PCIe link. Resolution To work around this problem, connect the PERST# to the i_gpio_perst0_n port of the GTS AXI Streaming FPGA IP for PCI Express, tie the p0_pin_perst_n_i port to logic high. Assign the i_gpio_perst0_n port to either one of the reset pins location in the corresponding HVIO bank. The other reset pins not used as PERST# can be connected as a generic HVIO signal. The i_gpio_perst0_n only releases PCIe HIP and GTS transceiver from reset after FPGA enters user mode. Hence CvP is not supported and may not reach Gen 1/2 L0 state within 100ms after PERST# deactivation during cold reset. In a future release of Quartus Prime Pro Edtion software, you can connect PERST# to the p0_pin_perst_n_i port (assign to one of the reset pins locations in the HVIO bank). However, the other reset pin in HVIO cannot be connected on PCB. These limitations will be fixed in production devices.Why does a Quartus® Prime Software design that contains both the HDMI 2.0 IP and the HDMI 2.1 IP encounter a Quartus® Prime Software synthesis error?
Description Due to a problem starting from the Quartus® Prime Pro Edition Software v19.4, you may see a Quartus® Prime Software synthesis error if both the HDMI 2.0 IP and the HDMI 2.1 IP are instantiated in the same Quartus® Prime Software project. Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. This problem is due to both the HDMI 2.0 IP and the HDMI 2.1 IP being generated with the same IP library file name by default. Resolution To work around this problem, edit either the HDMI 2.0 IP <design>.qip or the HDMI 2.1 IP <design>.qip files to ensure that each HDMI IP core is compiled using its own unique IP library filename. Follow the following instructions: 1. Edit either the HDMI 2.0 IP or the HDMI 2.1 IP QIP file The location of QIP file is in <Quartus_roject>/<hdmi_ip>/hdmi_ip.qip 2. Search for " -library "altera_hdmi_XXXX" " and replace all with " -library "altera_hdmi_XXXX_YY" " For example, search for -library "altera_hdmi_1961" and replace with -library "altera_hdmi_1961_20" 3. Save the modified QIP file and proceed to compile the Quartus® Prime Software project as usual.Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?
Description Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4, you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode. This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why does the Cadence Xcelium* simulator fail when using Dynamic Reconfiguration IP with PTP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, Agilex™ 7 F-Tile Dynamic reconfiguration IPs with PTP may show errors when using the Cadence Xcelium* simulator, similar to the error shown below: xmelab: *E,CUVIMG (../hardware_test_design/support_logic/eth_f_hw_auto_tiles.sv,23321|341): Implicit name not allowed in hierarchical name. Resolution There is no workaround.Why is video flickering or a white display observed when using the F-Tile SDI II FPGA IP and GTS SDI II IP parallel loopback with the external VCXO Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, the F-Tile SDI II FPGA IP and GTS SDI II IP parallel loopback with external VCXO Design Example has video flickering or a white display. This problem only occurs when testing with a 48Hz refresh rate. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why do F-Tile variants with PTP and Tx PTP classifier enabled within the Ethernet Subsystem Intel® FPGA IP fail to compile when using the Synopsys* VCS simulator?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2, F-Tile variants with PTP and PTP packet classifier enabled within the Ethernet Subsystem Intel® FPGA IP will fail to compile when using the Synopsys* VCS simulator. This problem does not affect other supported simulators. Resolution To workaround this problem, add the “-ignore initializer_driver_checks” switch to the USER_DEFINED_ELAB_OPTIONS section of the run_vcs.sh file found in the <example design project name>/example_testbench directory. This problem was fixed in version 23.3 of the Intel® Quartus® Prime Pro Edition Software.