Why does the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example may fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled. Resolution To work around this problem in the Intel® Quartus® Prime Pro Software version 22.1 and earlier, launch the Design Space Explorer II in the Intel® Quartus® Prime Pro Software and perform seed sweeps. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why does the F-Tile Dynamic Reconfiguration Suite Intel® IP Design Example using VHDL fail to simulate correctly when using the Cadence® Xcellium simulator?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the VHDL design example implementation of the F-Tile Dynamic Reconfiguration Suite Intel® IP fails to simulate correctly. The Cadence® Xcellium simulator will generate warnings related to the dr_cpu_ctrl_inst module containing text similar to that shown below: Attempted propagation of defparam results to a non-Verilog instance Resolution To work around this problem in simulation, edit the run_xcelium.sh file to add a new -generic switch to force and set the dr_cpu_ctrl DMEM_INIT_FILE with the correct *_combined mif file generated from QTLG flow. Note: Ensure that the correct mif file name has been used only after the Quartus Support-logic Generation stage has run. An example of the required assignment is shown below: xmelab -relax -timescale '1 ps / 1 ps' -access +rwc -generic "basic_avl_tb_top.eth_f_hw.dr_dut:dr_f_0.dr_cpu_ctrl_inst:DMEM_INIT_FILE => \"eth_f_hw__combined_z1577a_x0_y166_n0.mif\"" basic_avl_tb_top This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why is '256-bit' the only option available for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express*
Description Starting with the Intel® Quartus® Prime Pro Edition Software version 21.4, the '64-bit' option for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express* is no longer available. Resolution To migrate an L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* instance from a '64-bit' 'Application Interface Width' configuration to a '256-bit' 'Application Interface Width' configuration. Open the Platform Designer system where the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* is instantiated. Under the 'System Settings' tab make the following changes: Set the 'Application Interface Width' parameter to '256-bit'. Set the 'Hard IP Mode' parameter to the same configuration but using a '256-bit' interface. Under the 'Avalon-MM Settings' tab make the following changes: Set the 'Avalon-MM address width' to '64-bit'. If the 'Enable non-bursting Avalon-MM Slave interface with individual byte access (TXS)' parameter is set to 'ON', adjust the 'Address width of accessible PCIe memory space (TXS)' to accommodate the new address range of the system. Go to the 'System' menu and select the 'Assign Base Address' option. Platform Designer will rearrange the system address map to accommodate the changes. Save the Platform Designer system. Regenerate the Platform Designer system.
Why Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled the active serial programming feature. Is my Development Cable affected by this? If your USB Blaster III Development cable has a serial number ranging from UB3000000 - UB3006090, then you will need to update the PID. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”Why does it take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and Standard Edition software version 21.1 and earlier, it might take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard. This problem might occur when the clock sources of the rx_coreclk and the xcvr_refclk in the SDI II Intel FPGA IP are 0 ppm tolerance. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 18.1. Download and install patch 0.23std from the appropriate link below, then re-generate your programming file. Download patch 0.23std for Windows (Quartus-18.1std-0.23std-windows.exe) Download patch 0.23std for Linux (Quartus-18.1std-0.23std-linux.run) Download the Readme for patch 0.23std (Quartus-18.1std-0.23std-readme.txt) This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro/Standard Edition Software.What are the special requirements of Intel Agilex® 7 F-Tile devices reference clocks?
Description The Intel Agilex® 7 F-Tile devices reference clocks have special requirements that users must follow. Otherwise, your design will work abnormally, and transceivers might experience performance degradation. FHT Reference Clock: You must provide a stable and running reference clock to FHT PMA at device configuration. Otherwise, it will cause FHT PMA lane performance degradation. Once the FHT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FHT PMA lane performance degradation, and you must reconfigure the device to get the design working normally. The FHT reference clock stable definition is specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet. FGT Reference Clock: When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You must provide a stable and running reference clock to FGT at device configuration. Otherwise, it will cause FGT PMA lane performance degradation. Once the FGT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FGT PMA lane performance degradation. When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You can provide a stable and running reference clock to FGT after device configuration. After the FGT reference clock is up, it can be inactive. The FGT reference clock stable definition is specified in Intel Agilex 7 FPGAs and SoCs Device Data Sheet. System PLL Reference Clock: When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You must provide a stable and running reference clock to the system PLL at device configuration. Otherwise, the system PLL will not lock, and you must reconfigure the device to get the device working normally. Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally. When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You can provide a stable and running reference clock to system PLL after device configuration. Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally. The System PLL reference clock stable definition Must adhere to the F-Tile FGT Reference Clock Input Specifications specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet. Reference clock maximum period jitter must be less than +/-2.5%. For more details, please refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. Resolution Users must adhere to the aforementioned requirements without any exceptions.Why does a Quartus® Prime Software design that contains both the HDMI 2.0 IP and the HDMI 2.1 IP encounter a Quartus® Prime Software synthesis error?
Description Due to a problem starting from the Quartus® Prime Pro Edition Software v19.4, you may see a Quartus® Prime Software synthesis error if both the HDMI 2.0 IP and the HDMI 2.1 IP are instantiated in the same Quartus® Prime Software project. Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. This problem is due to both the HDMI 2.0 IP and the HDMI 2.1 IP being generated with the same IP library file name by default. Resolution To work around this problem, edit either the HDMI 2.0 IP <design>.qip or the HDMI 2.1 IP <design>.qip files to ensure that each HDMI IP core is compiled using its own unique IP library filename. Follow the following instructions: 1. Edit either the HDMI 2.0 IP or the HDMI 2.1 IP QIP file The location of QIP file is in <Quartus_roject>/<hdmi_ip>/hdmi_ip.qip 2. Search for " -library "altera_hdmi_XXXX" " and replace all with " -library "altera_hdmi_XXXX_YY" " For example, search for -library "altera_hdmi_1961" and replace with -library "altera_hdmi_1961_20" 3. Save the modified QIP file and proceed to compile the Quartus® Prime Software project as usual.Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies?
Description Due to a problem in In the Intel® Quartus® Prime Pro Edition Software versions 22.2 and earlier, you might observe the F-tile Reference and System PLL clocks Intel® FPGA IP fails to lock at: 999.9 MHz with the reference clock frequency set as 323.2 MHz. 506.88 MHz with the reference clock frequency set as 245.76 MHz. Resolution To work around this problem, you need to do the following steps: In the project navigator, double-click the OPN (ordering part number). In the pop-out window, click the “Device and Pin Options” button. In the “General” category, change the “Configuration clock source” parameter from “Internal Oscillator” to: 100 MHz OSC_CLK_1 pin, or 125 MHz OSC_CLK_1 pin Recompile the design. Provide an external reference clock with the correct frequency to the OSC_CLK_1 pin. The “OSC_CLK_1” pin location can be found in the schematics of your development kit. Note: for Intel Agilex® F-tile devices with OPNs that end with the suffix VR0, VR1, and VR2, you need to use Intel® Quartus® Prime Programmer version 21.4 to get the above workarounds working.Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?
Description Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4, you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode. This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.