Why is '256-bit' the only option available for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express*
Description Starting with the Intel® Quartus® Prime Pro Edition Software version 21.4, the '64-bit' option for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express* is no longer available. Resolution To migrate an L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* instance from a '64-bit' 'Application Interface Width' configuration to a '256-bit' 'Application Interface Width' configuration. Open the Platform Designer system where the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* is instantiated. Under the 'System Settings' tab make the following changes: Set the 'Application Interface Width' parameter to '256-bit'. Set the 'Hard IP Mode' parameter to the same configuration but using a '256-bit' interface. Under the 'Avalon-MM Settings' tab make the following changes: Set the 'Avalon-MM address width' to '64-bit'. If the 'Enable non-bursting Avalon-MM Slave interface with individual byte access (TXS)' parameter is set to 'ON', adjust the 'Address width of accessible PCIe memory space (TXS)' to accommodate the new address range of the system. Go to the 'System' menu and select the 'Assign Base Address' option. Platform Designer will rearrange the system address map to accommodate the changes. Save the Platform Designer system. Regenerate the Platform Designer system.Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies?
Description Due to a problem in In the Intel® Quartus® Prime Pro Edition Software versions 22.2 and earlier, you might observe the F-tile Reference and System PLL clocks Intel® FPGA IP fails to lock at: 999.9 MHz with the reference clock frequency set as 323.2 MHz. 506.88 MHz with the reference clock frequency set as 245.76 MHz. Resolution To work around this problem, you need to do the following steps: In the project navigator, double-click the OPN (ordering part number). In the pop-out window, click the “Device and Pin Options” button. In the “General” category, change the “Configuration clock source” parameter from “Internal Oscillator” to: 100 MHz OSC_CLK_1 pin, or 125 MHz OSC_CLK_1 pin Recompile the design. Provide an external reference clock with the correct frequency to the OSC_CLK_1 pin. The “OSC_CLK_1” pin location can be found in the schematics of your development kit. Note: for Intel Agilex® F-tile devices with OPNs that end with the suffix VR0, VR1, and VR2, you need to use Intel® Quartus® Prime Programmer version 21.4 to get the above workarounds working.What are the special requirements of Intel Agilex® 7 F-Tile devices reference clocks?
Description The Intel Agilex® 7 F-Tile devices reference clocks have special requirements that users must follow. Otherwise, your design will work abnormally, and transceivers might experience performance degradation. FHT Reference Clock: You must provide a stable and running reference clock to FHT PMA at device configuration. Otherwise, it will cause FHT PMA lane performance degradation. Once the FHT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FHT PMA lane performance degradation, and you must reconfigure the device to get the design working normally. The FHT reference clock stable definition is specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet. FGT Reference Clock: When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You must provide a stable and running reference clock to FGT at device configuration. Otherwise, it will cause FGT PMA lane performance degradation. Once the FGT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FGT PMA lane performance degradation. When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You can provide a stable and running reference clock to FGT after device configuration. After the FGT reference clock is up, it can be inactive. The FGT reference clock stable definition is specified in Intel Agilex 7 FPGAs and SoCs Device Data Sheet. System PLL Reference Clock: When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You must provide a stable and running reference clock to the system PLL at device configuration. Otherwise, the system PLL will not lock, and you must reconfigure the device to get the device working normally. Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally. When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP You can provide a stable and running reference clock to system PLL after device configuration. Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally. The System PLL reference clock stable definition Must adhere to the F-Tile FGT Reference Clock Input Specifications specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet. Reference clock maximum period jitter must be less than +/-2.5%. For more details, please refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. Resolution Users must adhere to the aforementioned requirements without any exceptions.Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?
Description Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4, you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode. This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why does it take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and Standard Edition software version 21.1 and earlier, it might take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard. This problem might occur when the clock sources of the rx_coreclk and the xcvr_refclk in the SDI II Intel FPGA IP are 0 ppm tolerance. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 18.1. Download and install patch 0.23std from the appropriate link below, then re-generate your programming file. Download patch 0.23std for Windows (Quartus-18.1std-0.23std-windows.exe) Download patch 0.23std for Linux (Quartus-18.1std-0.23std-linux.run) Download the Readme for patch 0.23std (Quartus-18.1std-0.23std-readme.txt) This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro/Standard Edition Software.Why does the O-RAN Intel® FPGA IP give incorrect values when the Mu-law compression is turned on?
Description Due to a problem in the O-RAN Intel® FPGA IP version 1.8.0 and earlier, you may see the O-RAN Intel FPGA IP gives incorrect values when the Mu-law compression is turned on. When the compressed IqWidth and the original PRB value combination match as per below, the O-RAN Intel FPGA IP may generate an incorrect value of compressed PRB. IqWidth 8: Original PRB Value 0xFFC0 IqWidth 9: Original PRB Value 0xFFE0 IqWidth 10: Original PRB Value 0xFFF0 IqWidth 11: Original PRB Value 0xFFF8 IqWidth 12: Original PRB Value 0xFFFC IqWidth 13: Original PRB Value 0xFFFE IqWidth 14: Original PRB Value 0xFFFF For example, the original PRB value "0xFFF8" is compressed to 11 bits with comp Shift value '0' and the compressed PRB value is incorrectly generated as 0 (0x0). The correct compressed PRB value should be -1 (0x7FF). The Fronthaul Compression Intel® FPGA IP has the same problem. Resolution This problem is scheduled to be fixed in the O-RAN Intel® FPGA IP Version 1.8.1 and the Fronthaul Compression Intel FPGA IP 1.0.4.Why are the HSSI parameter settings for the TX Equalizer in the Agilex™ 5 FPGA GTS transceiver configured incorrectly?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you might see HSSI parameter settings for TX Equalizer in the Agilex™ 5 FPGA GTS transceiver are not configured correctly when you try to set the TX Equalizer parameters setting in the Quartus Prime settings file (.qsf) or by using the Assignment Editor tool. The affected HSSI parameter settings for the TX Equalizer in the Agilex™ 5 FPGA GTS transceiver that are set using the method mentioned above include the main_tap, pre_tap_1, pre_tap_2, and post_tap values. Resolution To work around this problem, perform a direct register write to update the GTS TX Equalizer register value during user mode. The offset register address information for the TX Equalizer settings can be found in the Agilex™ 5 FPGA GTS Transceiver PHY User Guide, under the register map section GTS PMA/FEC Direct PHY IP Register Map. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.
Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”Why does the "o_rx_error" port of the E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core not reflect oversized frames in transmission?
Description Due to a fault in the 100G E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core RX status detection logic, you might observe oversized frames ( default maximum frame size in IP setting is 1518), fail to cause the relative bit of port o_rx_error to assert to reflect oversized frame behavior. Resolution There is no plan to fix this issue in future IP release. You can use statistic register(0x924/0x925) to monitor whether there is oversized frame in transmission.Why do the Agilex™ 7 FPGA devices fail to reconfigure after the F-tile System PLL reference clock has a temporary loss?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1 and earlier, if your F-tile System PLL reference clock experiences discontinuity or a temporary loss condition, you might observe that the Agilex™ 7 FPGA device fails to reconfigure. Altera recommends you provide a stable reference clock throughout the design operation once your reference clock for the F-tile System PLL is available. If you cannot adhere to this, you must reconfigure the device. Resolution To work around this problem, you should try configuring your device again if your first reconfiguration fails.