Why do we see the error message about "Malformed TLP packet"?
Description Due to a problem in the Intel® Stratix® 10 PCI Express* Root Port example design with MSI, the Intel® Stratix® 10 HPS PCI Express Root Port can't mount Micron 2100AI NVME SSD, and a "Malformed TLP packet" message is shown during the boot up. Resolution To work around this problem in the Intel® Stratix® 10 PCI Express* Root Port example design with MSI, add the below code in the "s10_tlp_read_packet" function in file drivers/pci/controller/pcie-altera.c for (i = 0; i < 5; i++) { ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); dw[count-1] = cra_readl(pcie, S10_RP_RXCPL_REG); printk("status %x data %x\n",ctrl,dw[count-1]); if (ctrl & RP_RXCPL_EOP) { return PCIBIOS_SUCCESSFUL; } } dev_warn(dev, "Malformed TLP packet\n");
Why o_rx_pcs_fully_aligned does not assert for 40GE-4 Advanced mode F-Tile Ethernet Hard IP design when Custom Ethernet line rate > 63Gbps?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might observe o_rx_pcs_fully_aligned does not assert for the F-Tile Ethernet Hard IP design with below configurations: Advanced mode: Enabled Ethernet mode: 40GE-4 Custom Ethernet line rate: > 63 Gbps Resolution There is no workaround. There is no fix planned in the future. When advanced mode enabled for 40GE-4 design, supported custom Ethernet line rate is: 41.25~63 Gbps.Why is there a mismatch in the PFC width between the theory calculation and the hardware measurement in the F-tile Ethernet Hard IP design?
Description You might observe a mismatch in the PFC width between the theory calculation and hardware measurement at max PFC quanta. This is due to the alignment marker (AM) pulse window within the PCS data, which is causing this variation. Resolution Estimating the deviation of the PFC width from the expected value is impossible. Quanta variation is not quantifiable, and the variation is expected. There is no plan to fix this problem.Why am I seeing Deterministic Latency Accuracy problems when using Inter-protocol Designs in the GTS Dynamic Reconfiguration Controller IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, you may inter-protocol GTS Ethernet Hard IP with PTP and GTS CPRI IP in GTS Dynamic Reconfiguration Controller IP designs. Resolution Currently, there is no workaround for this problem. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software. Related IP Core GTS Dynamic Reconfiguration Controller IP GTS Ethernet Hard IP with PTP GTS CPRI IPWhy do the Agilex™ 7 FPGA devices fail to reconfigure after the F-tile System PLL reference clock has a temporary loss?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1 and earlier, if your F-tile System PLL reference clock experiences discontinuity or a temporary loss condition, you might observe that the Agilex™ 7 FPGA device fails to reconfigure. Altera recommends you provide a stable reference clock throughout the design operation once your reference clock for the F-tile System PLL is available. If you cannot adhere to this, you must reconfigure the device. Resolution To work around this problem, you should try configuring your device again if your first reconfiguration fails.Why does a Quartus® Prime Software design that contains both the HDMI 2.0 IP and the HDMI 2.1 IP encounter a Quartus® Prime Software synthesis error?
Description Due to a problem starting from the Quartus® Prime Pro Edition Software v19.4, you may see a Quartus® Prime Software synthesis error if both the HDMI 2.0 IP and the HDMI 2.1 IP are instantiated in the same Quartus® Prime Software project. Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. This problem is due to both the HDMI 2.0 IP and the HDMI 2.1 IP being generated with the same IP library file name by default. Resolution To work around this problem, edit either the HDMI 2.0 IP <design>.qip or the HDMI 2.1 IP <design>.qip files to ensure that each HDMI IP core is compiled using its own unique IP library filename. Follow the following instructions: 1. Edit either the HDMI 2.0 IP or the HDMI 2.1 IP QIP file The location of QIP file is in <Quartus_roject>/<hdmi_ip>/hdmi_ip.qip 2. Search for " -library "altera_hdmi_XXXX" " and replace all with " -library "altera_hdmi_XXXX_YY" " For example, search for -library "altera_hdmi_1961" and replace with -library "altera_hdmi_1961_20" 3. Save the modified QIP file and proceed to compile the Quartus® Prime Software project as usual.Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?
Description Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4, you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode. This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why is a link-up error seen in simulation using the F-Tile Ethernet FPGA Hard IP when used in the MACsec FPGA IP System Example Design?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, the F-Tile Ethernet FPGA Hard IP shows a link-up error, causing the transmitter reset to acknowledge and transmitter lanes stability to fail. This problem is seen in designs that are custom made as in the MACsec FPGA IP System Example Design. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.Why can’t I configure the GTS PMA/FEC Direct PHY IP into Internal serial loopback mode when the Transceiver RX Adaptation mode is set to manual mode?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when the RX adaptation mode is set to manual, you cannot enable the internal serial loopback feature, as this will cause functional failure of the GTS transceiver. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.Why does toggling p0_pin_perst_n_i fail to reset PCI Express links in the Agilex™ 5 ES devices in the Quartus® Prime Pro Edition Software version 24.1?
Description For a PCIe link in a transceiver bank, there are two pins in HVIO banks with optional function as pin perst for the PCIe link. You can connect PERST# to either one of the reset pins. For the reset pin not used as PERST#, it can be used as a generic HVIO signal. For example, if pin PIN_PERST_N_CVP_L1A_0 in Bank 5A is assigned as PERST# for the PCIe link in Bank L1A, pin PIN_PERST_N_CVP_L1A_1 in Bank 5B can be assigned as a generic HVIO signal. Due to a problem in the ES devices, assigning any of the two reset pins as PERST# fails to reset the PCIe link. Resolution To work around this problem, connect the PERST# to the i_gpio_perst0_n port of the GTS AXI Streaming FPGA IP for PCI Express, tie the p0_pin_perst_n_i port to logic high. Assign the i_gpio_perst0_n port to either one of the reset pins location in the corresponding HVIO bank. The other reset pins not used as PERST# can be connected as a generic HVIO signal. The i_gpio_perst0_n only releases PCIe HIP and GTS transceiver from reset after FPGA enters user mode. Hence CvP is not supported and may not reach Gen 1/2 L0 state within 100ms after PERST# deactivation during cold reset. In a future release of Quartus Prime Pro Edtion software, you can connect PERST# to the p0_pin_perst_n_i port (assign to one of the reset pins locations in the HVIO bank). However, the other reset pin in HVIO cannot be connected on PCB. These limitations will be fixed in production devices.