Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA

Hello Bhanu Pratap,

For the HPS design, the system uses a two-phase configuration process.

When programming the initial binary, only the HPS component is configured. During the subsequent boot process, the FPGA core must be loaded separately. SignalTap can only detect signals after the FPGA core has been successfully loaded.

I am not certain whether your current boot script handles this sequence correctly. As a simple validation, I recommend changing the design to use FPGA-first boot mode and recompile the project.

To do this, please open Device Settings in Quartus and change the configuration order to After INIT_DONE.

If this approach works, please let me know how you are currently booting the system in Linux, and I can guide you on the correct procedure to load the FPGA core.

Best regards,
Shun Jing

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