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aJan's avatar
aJan
Icon for New Contributor rankNew Contributor
29 days ago

Agilex5 HPS2FPGA usage

Hello,
I have an Agilex 5E 065B devkit board with Part Number A5ED065BB32AE6SR0. I have created a design in quartus that uses HPS2FPGA communication. I tested the design extensively and now want to configure the FPGA. However, it is not clear to me how the workflow has to be in that case after reading the documentation: https://docs.altera.com/r/docs/814550/current/agilextm-5-fpga-e-series-065b-premium-development-kit-user-guide/overview .

Below I list my worklfow (which was not working out):

  • Phase 1: Resotre GSRD
    1. I have a compiling quartus design
    2. I download the official GSRD JIC from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz
    3. In quartus I open the JTAG programmer and connect the device to my local machine. I power on the device with SW27 set to OFF-OFF-OFF-OFF. After clicking "auto-detect", I right click my FPGA device and click "change file" and select the freshly downloaded jic file. I click "start" and wait till process is completed sccessfully.
    4. I insert the HPS board's SD card into my local machine and download the GSRD SD image from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/sdimage.tar.gz
    5. I rename the .wic file to a .img file. Then I use Win32DiskImager to flash the image to the SD card. After completion I insert the SD card back into the HPS board.
    6. I connect the vertical HPS board pin to my local machine and open PUTTY to target the COM port. A window opens, which stays blank.
    7. I set SW27 to OFF-ON-ON-OFF and power on the board. In PUTTY I can see the linux boot logs. I can log in as root without password.
  • Phase 2: 
    1. I download the U-BOOT hex that matches my device from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/u-boot-spl-dtb.hex
    2. I open a NIOS shell and create a .jic file based on my designs rbf, by typing the command:
      quartus_pfg -c <my_project>.sof <my_project>.jic -o device=MT25QU128 -o flash_loader=A5ED065BB32AR0 -o hps_path=<hex_file_path> -o mode=ASX4 -o hps=1
    3. This created a .hps.jic file. I set SW27 back to OFF-OFF-OFF-OFF and connect to my local machine and power on the board. In quartus I again configure my newly created jic to the board via JTAG chain. 
    4. After completion I power off the board and set SW27 back to OFF-ON-ON-OFF. I open a PUTTY window and power on the board. However, this time the PUTTY window stays quiet even after several minutes. So I guess the boot is not happening correctly.

I would like to know if there is a substantial error in my workflow or, if there might be a problem in my quartus settings maybe (I have set configuration order to HPS first). I would be very glad if someone could help me with that. Feel free to tell me if any kind of log or additional information is required for understanding the error.

1 Reply

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    15 days ago

    Hi aJan,

    May I ask whether are you trying to use HPS or Nios for your design, as first phase it is HPS based, then 2nd phase you're using Nios Shell to run the quartus file generation?

    If you're using HPS, perhaps this guide will help (it is based on 24.1 since you're using 24.05)

    https://altera-fpga.github.io/rel-24.1/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/#build-sd-card-boot-binaries

    I suspect is because you're using the precompiled version of u-boot-spl.dtb.hex thus you're seeing some boot failures here, as any hardware mismatch between the precompiled configuration based on precompiled design vs the design that you have will result in error as it needs to matched correctly

    Could you try recompile the u-boot-spl-dtb.hex first following the guide on top, its compiled as part of yocto build and then proceed with the rest of the sequence per the guide. May I know your Quartus pro version as well? Usually we will advise to use the matching Quartus version with the release baseline.

     Thanks

    Kian