The FIFO has no output waveform

Hi, Richard.
Thank you for your assistance.
Then I have no further questions regarding this part.

There is a similar case reported by other users. You may refer to the solution provided in the following link:
https://community.altera.com/discussions/quartus-prime/warning---signal-not-found-in-vcd-error-message-with-quartus-prime-lite-edition-/311579

Here are a few troubleshooting steps you can try:
1. Try opening the project using a different version of Quartus and simulate it again.
(Please archive the project as a backup: Project > Archive Project)

2. Check if starting the new project from scratch helps resolve the issue.

3. Consider deleting the quartus2.qreg file.
The quartus2.qreg file stores user GUI settings and preferences. These preferences are not critical to the functionality of the software, so it is safe to delete the file. 
However, this will reset saved preferences such as window size/position, table column sorting/filtering, colors, etc.

4. You may also consider reinstalling Quartus to see if that resolves the issue.

Additionally, I recommend simulating using the Questa simulator tool directly instead of the Simulation Waveform Editor (University Program WVF). As it is a legacy tool. 

Regards,
Richard Tan
 

Dear Richard,

Thank you for your reply and for providing the relevant information.

As per your recommendation, I plan to switch to the Questa simulation tool for design verification.

I have used Questa previously. However, after completing the compilation, when I proceeded directly to RTL simulation, I noticed that upon opening the "work" folder within the program and selecting my project, no content was displayed.

Regarding this issue, are there any specific setup procedures that need to be performed before running the simulation? Do you have any instructional videos or documentation that I can refer to?

This is my first time using the Intel Quartus Prime Lite 24.1 version.

Thank you for your assistance.

Dear Richard,

Thank you for your guidance. Regarding the previous issue, the necessary settings were indeed related to the Testbench options.

Currently, I am directly using the generated .V (Verilog) file from the configured FIFO IP Core for simulation, rather than creating a separate Testbench file.

I would like to inquire about how to configure the Data Bus input in Questa – Intel FPGA Starter Edition to ensure that a new value is input at a fixed time interval (or fixed timing) for each clock cycle.

Thank you for your assistance.

Hi, Richard,

I sincerely appreciate your assistance. When using only the IP core, I attempted to use AI to help generate the necessary testbench file last night, and it ran successfully. I was able to observe the desired waveform results.

However, my application requires changing the enable logic state of the sclr pin on the IP core. The original active high needs to be changed to active low.

Yesterday, I tried using the block editor to add an extra NOT gate to the sclr pin of the FIFO block (the IP core). I then used the command “create hdl design file from current file” to convert the BDF file designed in the block editor into a .V (Verilog code) file. Subsequently, when using this modified file, the waveform did not appear.

In this regard, is my approach correct, or is there another proper method?

Thank you.

Hi Richard,

Regarding the issue with the FPGA waveform simulation output, I've found that it works for some projects but not for others. After cross-referencing, I have determined that the problem is likely related to incorrect instance name mapping in the testbench.

I have one final question. I am using a 10M02SCM153C8G FPGA. I wrote a simple program, successfully programmed it onto the development board, and confirmed it produced the intended simple functionality. However, I've noticed that whenever I power cycle the evaluation board (by unplugging and replugging the USB cable), the board reverts to running the original sample code that was pre-loaded.

This leads me to believe that although I performed the programming operation, the code was not actually programmed into the FPGA's non-volatile memory. Is there a specific option in the programming interface that I must select to ensure the code is permanently written to the FPGA's internal Configuration Flash Memory (CFM) block?

As I recall, the MAX 10 series does not require an external SPI EEPROM for configuration, which I believe is correct. Does this also mean that if I do not select the correct programming option, the code is only loaded into the FPGA's volatile SRAM, and is therefore lost upon power-off?