Forum Discussion
Occasional ContributorThe FIFO has no output waveform
Occasional ContributorDear Richard,
Thank you for your guidance. Regarding the previous issue, the necessary settings were indeed related to the Testbench options.
Currently, I am directly using the generated .V (Verilog) file from the configured FIFO IP Core for simulation, rather than creating a separate Testbench file.
I would like to inquire about how to configure the Data Bus input in Questa – Intel FPGA Starter Edition to ensure that a new value is input at a fixed time interval (or fixed timing) for each clock cycle.
Thank you for your assistance.
- RichardT_altera
Super Contributor
Hi MartinMaa
To configure the data bus input in Questa, you will need a testbench file.
You can generate one using the Simulation Waveform Editor, or alternatively, you can use an AI tool to assist you with this.
For better understanding, we have a quick start guide for the Quartus Standard simulation flow, along with an example design that you can try out.
https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/open-the-example-design.html
p.s: The RTL Simulation feature in Quartus is also known as NativeLink Flow
https://www.intel.com/content/www/us/en/docs/programmable/683080/23-1/running-rtl-simulation-nativelink-flow.html
Regards,
Richard Tan
