Forum Discussion
MartinMaa
Occasional Contributor
Occasional ContributorThe FIFO has no output waveform
Hi, I am currently using Quartus Prime Lite 24.1 and the 10M02M153C8G device to implement an 8Kx9 SYNC FIFO. I generated the design directly using the IP CORE. Initially, my tests successfully produ...
RichardT_altera
Super Contributor
Super ContributorAssuming you are using the NativeLink simulation flow, have you run at least the "Analysis & Synthesis" stage with the newly generated Verilog file? Additionally, to be sure, check the RTL Viewer to see a graphical representation of the synthesis results. Sometimes, a connection might be missing in the BDF, and you may generate the Verilog file thinking it is correct.
If the design compiled successfully in Quartus and the RTL view looks correct, I suspect the issue might be caused by the testbench.
Regarding the waveform not appearing, could you provide a screenshot showing what it looks like?
Regards,
Richard Tan
RichardT_alteraSuper Contributor
Super ContributorLet me know if further assistance is needed or if the solution worked for you.
Regards,
Richard Tan
