The FIFO has no output waveform

Assuming you are using the NativeLink simulation flow, have you run at least the "Analysis & Synthesis" stage with the newly generated Verilog file? Additionally, to be sure, check the RTL Viewer to see a graphical representation of the synthesis results. Sometimes, a connection might be missing in the BDF, and you may generate the Verilog file thinking it is correct.

If the design compiled successfully in Quartus and the RTL view looks correct, I suspect the issue might be caused by the testbench.

Regarding the waveform not appearing, could you provide a screenshot showing what it looks like?

Regards,
Richard Tan