The FIFO has no output waveform

Dear Richard,

Thank you for your reply and for providing the relevant information.

As per your recommendation, I plan to switch to the Questa simulation tool for design verification.

I have used Questa previously. However, after completing the compilation, when I proceeded directly to RTL simulation, I noticed that upon opening the "work" folder within the program and selecting my project, no content was displayed.

Regarding this issue, are there any specific setup procedures that need to be performed before running the simulation? Do you have any instructional videos or documentation that I can refer to?

This is my first time using the Intel Quartus Prime Lite 24.1 version.

Thank you for your assistance.