Occasional Contributor
Occasional ContributorHi, Richard,
I sincerely appreciate your assistance. When using only the IP core, I attempted to use AI to help generate the necessary testbench file last night, and it ran successfully. I was able to observe the desired waveform results.
However, my application requires changing the enable logic state of the sclr pin on the IP core. The original active high needs to be changed to active low.
Yesterday, I tried using the block editor to add an extra NOT gate to the sclr pin of the FIFO block (the IP core). I then used the command “create hdl design file from current file” to convert the BDF file designed in the block editor into a .V (Verilog code) file. Subsequently, when using this modified file, the waveform did not appear.
In this regard, is my approach correct, or is there another proper method?
Thank you.
Super ContributorAssuming you are using the NativeLink simulation flow, have you run at least the "Analysis & Synthesis" stage with the newly generated Verilog file? Additionally, to be sure, check the RTL Viewer to see a graphical representation of the synthesis results. Sometimes, a connection might be missing in the BDF, and you may generate the Verilog file thinking it is correct.
If the design compiled successfully in Quartus and the RTL view looks correct, I suspect the issue might be caused by the testbench.
Regarding the waveform not appearing, could you provide a screenshot showing what it looks like?
Regards,
Richard Tan
Super ContributorLet me know if further assistance is needed or if the solution worked for you.
Regards,
Richard Tan
