SystemVerilog attribute with multi-line string has weird behavior

SystemVerilog 2005 (IEEE Std 1800-2005) Section 3.6 String literals says this:

A string literal must be contained in a single line unless the new line is immediately preceded by a \ (back slash). In this case, the back slash and the new line are ignored.

It seems that .sv should support backslash+newline inside string......

When I tried backslash-newline in module parameter like this:

(* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; -name VIRTUAL_PIN ON -to b[*]; -name VIRTUAL_PIN ON -to c[*]" *)
module top(
	input logic raw_clock,
 
	input logic[17:0] a,
	input logic[17:0] b,
	output logic[35:0] c
);
	logic clock;
	
	pll pll(
		.inclk0(raw_clock),
		.c0(clock)
	);
	
	lpm_mult #(
		.lpm_widtha(18),
		.lpm_widthb(18),
		.lpm_widthp(36),
		.lpm_pipeline(1),
		.lpm_representation("UNS\
IGNED")
	) mult(
		.clock(clock),
		.dataa(a),
		.datab(b),
		.result(c)
	);
endmodule

I got following error message:

Warning (272007): MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) lpm_mult|LPM_REPRESENTATION The value assigned is UNS
IGNED and the valid value list is UNSIGNED|SIGNED
Error (272006): Parameter error: LPM_REPRESENTATION parameter with value UNS
IGNED must be set to SIGNED or UNSIGNED

Whie it retains string type (i.e. not convertered to bitstream), it seems that the newline character is not ignored.

The following SystemVerilog source code, which includes type casting for attribute, caused crash (core dump) of quartus_map:

(* altera_attribute = string'("-name VIRTUAL_PIN ON -to a[*]; \
-name VIRTUAL_PIN ON -to b[*]; \
-name VIRTUAL_PIN ON -to c[*]") *)
module top(
	input logic raw_clock,
 
	input logic[17:0] a,
	input logic[17:0] b,
	output logic[35:0] c
);
	logic clock;
	
	pll pll(
		.inclk0(raw_clock),
		.c0(clock)
	);
	
	lpm_mult #(
		.lpm_widtha(18),
		.lpm_widthb(18),
		.lpm_widthp(36),
		.lpm_pipeline(1),
		.lpm_representation("UNSIGNED")
	) mult(
		.clock(clock),
		.dataa(a),
		.datab(b),
		.result(c)
	);
endmodule

The following source code, which uses concatenation operator for attribute, synthesised as expected without any errors.

(* altera_attribute = {
	"-name VIRTUAL_PIN ON -to a[*]; ",
	"-name VIRTUAL_PIN ON -to b[*]; ",
	"-name VIRTUAL_PIN ON -to c[*]"
} *)
module top(
	input logic raw_clock,
 
	input logic[17:0] a,
	input logic[17:0] b,
	output logic[35:0] c
);
	logic clock;
	
	pll pll(
		.inclk0(raw_clock),
		.c0(clock)
	);
	
	lpm_mult #(
		.lpm_widtha(18),
		.lpm_widthb(18),
		.lpm_widthp(36),
		.lpm_pipeline(1),
		.lpm_representation("UNSIGNED")
	) mult(
		.clock(clock),
		.dataa(a),
		.datab(b),
		.result(c)
	);
endmodule

As it seems that string concatenation is better option than backslash-newline idiom, I'll use this method. However, could you consider investigating this issue, especially the crashed case?

I'm pretty sure the language is SystemVerilog indeed.

• The file extension is ".sv" (instead of ".v")
• If it were Verilog mode, the keyword like 'logic' and/or 'always_ff' would be produce error.

I'm happy with Verilog concatenation operator, which I can handle arbitary long attributes as managable size.

Still, it seems that the crash during compile needs to be fixed.

It seems that you are saying "You should bear with random compiler crashes because you didn't buy it." My opinion is that If some feature is unsupported in free version, it should present (nice) error message, instead of random crash.

I mentioned that this source code caused crash (core dump) of quartus_map (which is different from very first source code):

(* altera_attribute = string'("-name VIRTUAL_PIN ON -to a[*]; \
-name VIRTUAL_PIN ON -to b[*]; \
-name VIRTUAL_PIN ON -to c[*]") *)
module top(
	input logic raw_clock,
 
	input logic[17:0] a,
	input logic[17:0] b,
	output logic[35:0] c
);
	logic clock;
	
	pll pll(
		.inclk0(raw_clock),
		.c0(clock)
	);
	
	lpm_mult #(
		.lpm_widtha(18),
		.lpm_widthb(18),
		.lpm_widthp(36),
		.lpm_pipeline(1),
		.lpm_representation("UNSIGNED")
	) mult(
		.clock(clock),
		.dataa(a),
		.datab(b),
		.result(c)
	);
endmodule

Disclaimer: I can accept that the very first source code of this thread is due to limit support of lite edition.

Thanks for handling the issue.

I apologize using harsh language; I thought the crash report was completely ignored.