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BLee15's avatar
BLee15
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SystemVerilog attribute with multi-line string has weird behavior

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition ​ ​ When I tried to synthesis following Verilog code: (* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; \ -name VIR...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I wouldn't think this is a bug. Backslash is a line extension for Tcl, not Verilog. You can add backslashes if you were to add these assignments to your .qsf file since that file is Tcl based. A .sv file is not.

#iwork4intel

BLee15's avatar
BLee15
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SystemVerilog 2005 (IEEE Std 1800-2005) Section 3.6 String literals says this:

A string literal must be contained in a single line unless the new line is immediately preceded by a \ (back slash). In this case, the back slash and the new line are ignored.

It seems that .sv should support backslash+newline inside string......