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BLee15's avatar
BLee15
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SystemVerilog attribute with multi-line string has weird behavior

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition ​ ​ When I tried to synthesis following Verilog code: (* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; \ -name VIR...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

As you show in your last example, you can just use whitespace (carriage return between words). There's no need to even use the backslash.

But did you check which language interpreter was being used as I mentioned?

#iwork4intel

  • BLee15's avatar
    BLee15
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    I'm pretty sure the language is SystemVerilog indeed.

    • The file extension is ".sv" (instead of ".v")
    • If it were Verilog mode, the keyword like 'logic' and/or 'always_ff' would be produce error.