Compiling quartus design of PCIe root port example failing in WSL2

I am trying to follow the instruction for the PCIe root port example design (https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/pcie_rp/ug-pcie_rp-agx5e-premium/).

I am able to compile the design for the branch rel/26.1 in my native windows install of Quartus (version 26.1), using
```powershell
git clone -b rel/26.1 https://github.com/altera-fpga/agilex5-ed-pcie-rp.git
cd .\agilex5-ed-pcie-rp\src\hw\a5e065bb32aea_mdk\syn\g4x4
C:\path\to\quartus_sh --flow compile top
```

but trying the same command in WSL2 with the linux install of the same Quartus version, I get compilation errors
```bash
git clone -b rel/26.1 https://github.com/altera-fpga/agilex5-ed-pcie-rp.git
cd .\agilex5-ed-pcie-rp\src\hw\a5e065bb32aea_mdk\syn\g4x4
/path/to/quartus_sh --flow compile top
```

The errors I get:
```
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(345): design library "hps_f2sdram" does not contain primary unit "hps_f2sdram" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 345
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(347): design library "hps_m" does not contain primary unit "hps_m" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 347
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(349): design library "jtag_subsys_address_span_extender_0" does not contain primary unit "jtag_subsys_address_span_extender_0" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 349
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(351): design library "jtag_subsys_mm_ccb_0" does not contain primary unit "jtag_subsys_mm_ccb_0" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 351
Error (13827): Ignored construct jtag_subsys_altera_mm_interconnect_1920_pikpq3i at jtag_subsys_altera_mm_interconnect_1920_pikpq3i.v(175) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/altera_mm_interconnect_1920/synth/jtag_subsys_altera_mm_interconnect_1920_pikpq3i.v Line: 175
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(357): design library "altera_mm_interconnect_1920" does not contain primary unit "jtag_subsys_altera_mm_interconnect_1920_pikpq3i" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 357
Error (13827): Ignored construct jtag_subsys_altera_mm_interconnect_1920_d6b64fi at jtag_subsys_altera_mm_interconnect_1920_d6b64fi.v(173) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/altera_mm_interconnect_1920/synth/jtag_subsys_altera_mm_interconnect_1920_d6b64fi.v Line: 173
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(359): design library "altera_mm_interconnect_1920" does not contain primary unit "jtag_subsys_altera_mm_interconnect_1920_d6b64fi" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 359
Error (13827): Ignored construct altera_reset_controller at altera_reset_controller.v(364) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_6c3i3ji/synth/ip/emif_io96b_hps_emif_io96b_hps_420_6c3i3ji/emif_io96b_hps_emif_io96b_hps_420_6c3i3ji_emif_0_ddr4comp/altera_reset_controller_1924/synth/altera_reset_controller.v Line: 364
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(361): design library "altera_reset_controller_1924" does not contain primary unit "altera_reset_controller" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 361
Error (13785): VHDL Use Clause error at jtag_subsys.vhd(363): design library "altera_reset_controller_1924" does not contain primary unit "altera_reset_controller" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 363
Error (13827): Ignored construct rtl at jtag_subsys.vhd(655) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 655
```

Opening the jtab_subsys.qsys file in platform designer I also get warnings about missing .ip files, among the missing ip files is the hps_f2sdram.ip file, I get a feeling that warning is related somehow.

I notice that in the windows native case the generated jtag_subsys file is generated as verilog, while in WSL it is a vhdl file. I do not why the same Quartus version and build numbers would fail in WSL while it succeeds in native windows.

Is there anyone who may understand what the differences might be?