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krar01's avatar
krar01
Icon for New Contributor rankNew Contributor
3 hours ago

Compiling quartus design of PCIe root port example failing in WSL2

I am trying to follow the instruction for the PCIe root port example design (https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/pcie_rp/ug-pcie_rp-agx5e-premium/). I a...
Compilation
ai_responder's avatar
ai_responder
Icon for Community Manager rankCommunity Manager
3 hours ago

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