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BLee15's avatar
BLee15
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SystemVerilog attribute with multi-line string has weird behavior

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition ​ ​ When I tried to synthesis following Verilog code: (* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; \ -name VIR...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

I had found out that information as below:

"To use the altera_attribute synthesis attribute in a Verilog Design File (.v) Definition or SystemVerilog Design File (.sv) Definition, add the attribute as a prefix to an object declaration using the Verilog 2001 attribute syntax (*...*). In addition, the synthesis attribute value must be a single string argument containing a list of QSF assignments separated by semicolons (;)"

Thanks