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BLee15's avatar
BLee15
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

SystemVerilog attribute with multi-line string has weird behavior

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition ​ ​ When I tried to synthesis following Verilog code: (* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; \ -name VIR...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi,

It is mentioned that random crashing behavior is observed in your previous reply, do you see a consistent error message for the error? I can see the same error message is issued by the software due to limited systemverilog language support in the Lite Edition of the software.

Thanks

  • BLee15's avatar
    BLee15
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    I mentioned that this source code caused crash (core dump) of quartus_map (which is different from very first source code):

    (* altera_attribute = string'("-name VIRTUAL_PIN ON -to a[*]; \
-name VIRTUAL_PIN ON -to b[*]; \
-name VIRTUAL_PIN ON -to c[*]") *)
module top(
	input logic raw_clock,
 
	input logic[17:0] a,
	input logic[17:0] b,
	output logic[35:0] c
);
	logic clock;
	
	pll pll(
		.inclk0(raw_clock),
		.c0(clock)
	);
	
	lpm_mult #(
		.lpm_widtha(18),
		.lpm_widthb(18),
		.lpm_widthp(36),
		.lpm_pipeline(1),
		.lpm_representation("UNSIGNED")
	) mult(
		.clock(clock),
		.dataa(a),
		.datab(b),
		.result(c)
	);
endmodule

    Disclaimer: I can accept that the very first source code of this thread is due to limit support of lite edition.