Occasional Contributor
Super ContributorWell, I guess I learned something today!
Perhaps it works in other parts of SV code but not in the middle of attributes. Have you tried that?
It might also be good to go into the Settings (from the Assignments menu) and under Verilog, make sure the SystemVerilog interpreter is set. Perhaps it's trying to synthesize your code as Verilog-2001 instead of SystemVerilog.
#iwork4intel
Occasional ContributorThe following source code, which uses concatenation operator for attribute, synthesised as expected without any errors.
(* altera_attribute = {
"-name VIRTUAL_PIN ON -to a[*]; ",
"-name VIRTUAL_PIN ON -to b[*]; ",
"-name VIRTUAL_PIN ON -to c[*]"
} *)
module top(
input logic raw_clock,
input logic[17:0] a,
input logic[17:0] b,
output logic[35:0] c
);
logic clock;
pll pll(
.inclk0(raw_clock),
.c0(clock)
);
lpm_mult #(
.lpm_widtha(18),
.lpm_widthb(18),
.lpm_widthp(36),
.lpm_pipeline(1),
.lpm_representation("UNSIGNED")
) mult(
.clock(clock),
.dataa(a),
.datab(b),
.result(c)
);
endmoduleAs it seems that string concatenation is better option than backslash-newline idiom, I'll use this method. However, could you consider investigating this issue, especially the crashed case?
