Forum Discussion
BLee15
Occasional Contributor
7 years agoSystemVerilog attribute with multi-line string has weird behavior
Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition When I tried to synthesis following Verilog code: (* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; \
-name VIR...
MEIYAN_L_Intel
Frequent Contributor
7 years agoHi,
May I know any update for this case?
Thanks
BLee15
Occasional Contributor
7 years agoI'm happy with Verilog concatenation operator, which I can handle arbitary long attributes as managable size.
Still, it seems that the crash during compile needs to be fixed.