Stratix III FPGA: Problem using Asynchronous FIFOs

how fast are we talking, and what fmax did Timequest tell you was the max speed?

The failure might be occuring accross the clock domain boundaries? IIRC, you have to tell timequest about these links yourself.

The frequencies I want to reach are: 200 MHz (CLK) and 280 MHz (CLK2). Fmax from Timequest are: 359.07 MHz (CLK) and 429.74 MHz (CLK2). I use a SDC file in Quartus where I set the time constrains: 4 ns for CLK and 3 ns for CLK2.

create_clock -period 4 -name clk [get_ports clk]

create_clock -period 3 -name clk2 [get_ports clk2]

derive_clock_uncertainty

Question: what is the phenomenon you notice in ModelSim to say it is not working at high speed?

Note that the FMax reported by Quartus applies for the internal register to register paths. The external input to register and register to output paths are not included, as they are governed by set_input_delay and set_output_delay SDC constraints.

Did you add a set_clock_groups to cut timing between the two clocks?

I'm using I/O files to test my design.First of all, Output Data aren't the same than Input Data. When I check the internal signals I see some control signals work wrong. Write and Read signals assert before Full and Empty ones (you can see it in the attached figure).

How are set_input_delay and set_output_delay used? What do you mean with set_clock_groups?

data_in probably has a set-up or hold violation, which explains the different output data.

For the additional SDC constraints you'd probably better read the manuals on TimeQuest.

There is another possible pitfall, I remember my colleague telling me that a dcfifo of depth 4 doesn't work well, hence he always uses a minimum depth of 8, I do too.

I've written a SDC file, I've compiled the design and it doesn't meet the timing constraints. I set the input and the output delays to zero. Have I written well the file?

# *******************************************************

# Created Clocks

# *******************************************************

create_clock -name clk -period 5 [get_ports clk]

create_clock -name clk2 -period 3.5 [get_ports clk2]

derive_clock_uncertainty

# *******************************************************

# Created Generated Clocks

# *******************************************************

derive_pll_clocks

# *******************************************************

# Set Clock Groups

# *******************************************************

set_clock_groups -asynchronous -group {clk} -group {clk2}

# *******************************************************

# Set False Paths

# *******************************************************

set_false_path -from [get_ports rst]

# *******************************************************

# Input Delays

# *******************************************************

set_input_delay -clock clk -max 0.0 [get_ports data_in[*]]

set_input_delay -clock clk -min 0.0 [get_ports data_in[*]]

set_input_delay -clock clk -max 0.0 [get_ports full_in]

set_input_delay -clock clk -min 0.0 [get_ports full_in]

set_input_delay -clock clk -max 0.0 [get_ports empty_in]

set_input_delay -clock clk -min 0.0 [get_ports empty_in]

# *******************************************************

# Output Delays

# *******************************************************

set_output_delay -clock clk -max 0.0 [get_ports wr[0]]

set_output_delay -clock clk -min 0.0 [get_ports wr[0]]

set_output_delay -clock clk2 -max 0.0 [get_ports wr[1]]

set_output_delay -clock clk2 -min 0.0 [get_ports wr[1]]

set_output_delay -clock clk2 -max 0.0 [get_ports rd[0]]

set_output_delay -clock clk2 -min 0.0 [get_ports rd[0]]

set_output_delay -clock clk -max 0.0 [get_ports rd[1]]

set_output_delay -clock clk -min 0.0 [get_ports rd[1]]

set_output_delay -clock clk -max 0.0 [get_ports full[0]]

set_output_delay -clock clk -min 0.0 [get_ports full[0]]

set_output_delay -clock clk2 -max 0.0 [get_ports full[1]]

set_output_delay -clock clk2 -min 0.0 [get_ports full[1]]

set_output_delay -clock clk2 -max 0.0 [get_ports empty[0]]

set_output_delay -clock clk2 -min 0.0 [get_ports empty[0]]

set_output_delay -clock clk -max 0.0 [get_ports empty[1]]

set_output_delay -clock clk -min 0.0 [get_ports empty[1]]

set_output_delay -clock clk2 -max 0.0 [get_ports data_mid[*]]

set_output_delay -clock clk2 -min 0.0 [get_ports data_mid[*]]

set_output_delay -clock clk -max 0.0 [get_ports data_out[*]]

set_output_delay -clock clk -min 0.0 [get_ports data_out[*]]

Looks quite OK to me.

You could do without the derive_pll_clocks, I believe you do not have a PLL in your design?

You can group pins together, so you have less typing to do: { wr[0] rd[0] full[0] ... } and the [get_ports ... ] is not necessary.

I usually set some small values for the input_delays, say -min 1.000 ns and -max 2.00 ns.

If it is a submodule I'm testing I don't care about the output delays and set them all as false-paths

What timing errors do you get?

I got setup errors in both clocks, but when I've removed the set_output_delay commands they have disappeared. Why does it happen?

I have got this frequencies: 224.52 MHz (CLK) and 378.36 MHz (CLK2). They seem too low for a design made from two FIFOs. What is the maximum frequency for the DCFIFO?

I generate the clocks using a testbench, have I to treat them as virtual clocks when I use the set_input_delay and set_output_delay commands?

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I got setup errors in both clocks, but when I've removed the set_output_delay commands they have disappeared. Why does it happen?

--- Quote End ---

Because it could not meet the requested output timing, i.e. it could not guarantee proper setup times for the external devices.

--- Quote Start ---

I have got this frequencies: 224.52 MHz (CLK) and 378.36 MHz (CLK2). They seem too low for a design made from two FIFOs. What is the maximum frequency for the DCFIFO?

--- Quote End ---

CLK has to deal with input signals, so it will have to factor in the input delays. Clk2 only deals with internal signals (as the output has a false path). Hence the difference bewteen the 2 clocks.

--- Quote Start ---

I generate the clocks using a testbench, have I to treat them as virtual clocks when I use the set_input_delay and set_output_delay commands?

--- Quote End ---

No they are real clocks, they just happen to be generated by a testbench.