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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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14 years ago

Question: what is the phenomenon you notice in ModelSim to say it is not working at high speed?

Note that the FMax reported by Quartus applies for the internal register to register paths. The external input to register and register to output paths are not included, as they are governed by set_input_delay and set_output_delay SDC constraints.

Did you add a set_clock_groups to cut timing between the two clocks?